Circuit 타이밍 시각화

패키지 버전

이 페이지의 코드는 다음 요구 사항을 사용하여 개발되었습니다. 아래 버전 이상을 사용하길 권장해요.

qiskit[all]~=2.3.0
qiskit-ibm-runtime~=0.43.1

Circuit의 명령어 시각화 외에도, Qiskit timeline_drawer 메서드를 사용하여 Circuit의 스케줄링을 시각화할 수 있습니다. 이 시각화는 예를 들어 Qubit의 유휴 시간을 빠르게 파악하는 데 도움이 될 수 있습니다. 다만, 이 메서드는 동적 Circuit에 대해 정확한 결과를 반환하지 않습니다. 동적 Circuit 스케줄링을 시각화하려면 Qiskit Runtime 지원 섹션에 설명된 draw_circuit_schedule_timing 메서드를 사용하세요.

예시

스케줄된 Circuit 프로그램을 시각화하려면, 일련의 제어 인수와 함께 이 함수를 호출할 수 있습니다. 출력 이미지의 대부분의 모양은 스타일시트로 수정할 수 있지만, 반드시 필요한 것은 아닙니다.

기본 스타일시트로 그리기

# Added by doQumentation — required packages for this notebook
!pip install -q qiskit qiskit-ibm-runtime

from qiskit import QuantumCircuit
from qiskit.visualization.timeline import draw
from qiskit.providers.fake_provider import GenericBackendV2
from qiskit.transpiler import generate_preset_pass_manager

qc = QuantumCircuit(2)
qc.h(0)
qc.cx(0, 1)

backend = GenericBackendV2(5)

pm = generate_preset_pass_manager(backend=backend, optimization_level=1)
isa_circuit = pm.run(qc)

draw(isa_circuit, target=backend.target)

프로그램 디버깅에 적합한 스타일시트로 그리기

from qiskit import QuantumCircuit
from qiskit.visualization.timeline import draw, IQXDebugging
from qiskit.providers.fake_provider import GenericBackendV2
from qiskit.transpiler import generate_preset_pass_manager

qc = QuantumCircuit(2)
qc.h(0)
qc.cx(0, 1)
qc.measure_all()

backend = GenericBackendV2(5)
pm = generate_preset_pass_manager(backend=backend, optimization_level=1)
isa_circuit = pm.run(qc)
draw(isa_circuit, style=IQXDebugging(), target=backend.target)

사용자 정의 generator 또는 layout 함수를 만들고, 기존 스타일시트를 해당 함수로 업데이트할 수 있습니다. 이렇게 하면 스케줄된 Circuit 드로어의 코드베이스를 수정하지 않고도 출력 이미지의 대부분의 모양을 제어할 수 있습니다. 더 많은 예시는 timeline_drawer API 레퍼런스를 참조하세요.

Qiskit Runtime 지원

Qiskit에 내장된 타임라인 드로어는 정적 Circuit에 유용하지만, 브로드캐스팅 및 분기 결정과 같은 암묵적인 작업으로 인해 동적 Circuit의 타이밍을 정확하게 반영하지 못할 수 있습니다. 동적 Circuit 지원의 일환으로, Qiskit Runtime은 요청 시 작업 결과 내에 정확한 Circuit 타이밍 정보를 반환합니다.

참고 사항

• 이것은 실험적인 함수입니다. 미리보기 출시 상태이므로 변경될 수 있습니다.
• 이 함수는 Qiskit Runtime Sampler 작업에만 적용됩니다.
• 총 Circuit 시간은 "compilation" 메타데이터에 반환되지만, 이는 청구에 사용되는 시간(양자 시간)이 아닙니다.

타이밍 데이터 검색 활성화

타이밍 데이터 검색을 활성화하려면, primitive 작업 실행 시 실험적 scheduler_timing 플래그를 True로 설정하세요.

from qiskit_ibm_runtime import QiskitRuntimeService, SamplerV2

service = QiskitRuntimeService()
backend = service.least_busy(operational=True, simulator=False)

pm = generate_preset_pass_manager(backend=backend, optimization_level=1)
isa_circuit = pm.run(qc)

sampler = SamplerV2(backend)
sampler.options.experimental = {
    "execution": {
        "scheduler_timing": True,
    },
}

sampler_job = sampler.run([isa_circuit])
result = sampler_job.result()

Circuit 타이밍 데이터 접근

요청 시, 각 PUB에 대한 Circuit 타이밍 데이터는 작업 결과 메타데이터의 ["compilation"]["scheduler_timing"]["timing"] 아래에 반환됩니다. 이 필드에는 원시 타이밍 정보가 포함되어 있습니다. 타이밍 정보를 표시하려면 타이밍 시각화 섹션에 설명된 내장 시각화 도구를 사용하세요.

첫 번째 PUB의 Circuit 타이밍 데이터에 접근하려면 다음 코드를 사용하세요:

job_result = sampler_job.result()
circuit_schedule = job_result[0].metadata["compilation"]["scheduler_timing"]
circuit_schedule_timing = circuit_schedule["timing"]

원시 타이밍 데이터 이해하기

draw_circuit_schedule_timing 메서드를 사용하여 Circuit 타이밍 데이터를 시각화하는 것이 가장 일반적인 사용 사례이지만, 반환된 원시 타이밍 데이터의 구조를 이해하면 유용할 수 있습니다. 이를 통해 예를 들어 정보를 프로그래밍 방식으로 추출하는 데 도움이 될 수 있습니다.

["compilation"]["scheduler_timing"]["timing"]에 반환되는 타이밍 데이터는 문자열 목록입니다. 각 문자열은 특정 채널의 단일 명령어를 나타내며, 다음 데이터 타입으로 쉼표로 구분됩니다:

• Branch - 명령어가 제어 흐름(then / else) 또는 메인 브랜치에 있는지 결정합니다.
• Instruction - 작동할 Gate와 Qubit입니다.
• Channel - 명령어가 할당된 채널입니다. 다음 중 하나일 수 있습니다:
  • Qubit x - Qubit _x_의 드라이브 채널입니다.
  • AWGRx_y (임의 파형 생성기 판독) - Qubit 측정 시 판독 채널에서 사용됩니다. x 및 y 인수는 각각 판독 장비 ID와 Qubit 번호에 해당합니다.
• T0 - 전체 스케줄 내에서 명령어의 시작 시간입니다.
• Duration - dt 초 단위의 명령어 지속 시간으로, 1 dt = 1 스케줄링 사이클입니다. Backend의 dt 값은 backend.dt를 사용하여 확인할 수 있습니다.
• Pulse - 사용 중인 펄스 작업의 유형입니다.

예시:

main,barrier,Qubit 0,7,0,barrier # A barrier on the main branch on qubit 0 at time 7 with 0 duration
main,reset_0,Qubit 0,7,64,play # A reset instruction on the main branch on qubit 0 at time 7 with duration 64 and a play operation
...

타이밍 시각화

qiskit-ibm-runtime v0.43.0 이상에서 Circuit 타이밍을 시각화할 수 있습니다. 타이밍을 시각화하려면 먼저 draw_circuit_schedule_timing 메서드를 사용하여 결과 메타데이터를 fig로 변환해야 합니다. 이 메서드는 plotly 그림을 반환하며, 직접 표시하거나, 파일로 저장하거나, 둘 다 할 수 있습니다. 사용할 plotly 명령에 대한 자세한 정보는 fig.show()와 fig.write_image("<path.format>")를 참조하세요.

from qiskit_ibm_runtime.visualization import draw_circuit_schedule_timing

# Create a figure from the metadata
fig = draw_circuit_schedule_timing(
    circuit_schedule=circuit_schedule_timing,
    included_channels=None,
    filter_readout_channels=False,
    filter_barriers=False,
    width=1000,
)

# Uncomment the following line to display the figure
# fig.show(renderer="notebook")

# Save to a file
# fig.write_html("scheduler_timing.html")

생성된 그림 이해하기

draw_circuit_schedule_timing이 출력하는 Circuit 타이밍 데이터 이미지는 다음 정보를 전달합니다:

• X축은 dt 초 단위의 시간이며, 1 dt = 1 스케줄링 사이클입니다. backend.dt를 사용하여 Backend의 dt 값을 확인할 수 있습니다.
• Y축은 채널입니다(채널은 펄스를 방출하는 장치로 생각하면 됩니다).
  • Receive channel - 그 자체로 장치가 아닌 유일한 채널입니다. 해당 시점에 허브와의 통신 절차에 참여하는 모든 채널에서 재생되는 명령입니다.
  • Qubit x - Qubit x의 드라이브 채널입니다.
  • AWGRx_y (임의 파형 발생기 읽기) - Qubit를 측정할 때 통신하기 위해 읽기 채널에서 사용됩니다. _x_와 y 인수는 각각 읽기 장치 ID와 Qubit 번호에 해당합니다.
  • Hub - 브로드캐스팅을 제어합니다.

또한 각 명령은 X_Y 형식을 가지며, X는 명령의 이름이고 Y는 펄스 유형입니다. play 유형은 제어 펄스를 적용하고, capture는 Qubit의 상태를 기록합니다. 각 명령 위에 마우스를 올려 더 자세한 정보를 확인할 수도 있습니다. 예를 들어, 이전 그림은 1161 dt에서 Qubit 10에 적용된 X Gate의 제어 펄스를 보여줍니다.

전체 예제

이 예제에서는 옵션을 활성화하고, 메타데이터에서 Circuit 타이밍 정보를 가져오고, 이미지로 표시하는 방법을 보여줍니다.

먼저 환경을 설정하고, Circuit을 정의하고 ISA Circuit으로 변환한 다음, 작업을 정의하고 실행합니다.

from qiskit_ibm_runtime import SamplerV2, QiskitRuntimeService
from qiskit.circuit import QuantumCircuit, QuantumRegister, ClassicalRegister
from qiskit.transpiler import generate_preset_pass_manager

service = QiskitRuntimeService()
backend = service.least_busy(operational=True, simulator=False)

# Create a dynamic circuit

qubits = QuantumRegister(1)
clbits = ClassicalRegister(1)
qc = QuantumCircuit(qubits, clbits)
(q0,) = qubits
(c0,) = clbits

qc.h(q0)
qc.measure(q0, c0)
with qc.if_test((c0, 1)):
    qc.x(q0)
qc.measure(q0, c0)

# Convert to an ISA circuit for the given backend

pm = generate_preset_pass_manager(backend=backend, optimization_level=1)
isa_circuit = pm.run(qc)

# Generate samplers for backend targets
sampler = SamplerV2(backend)
sampler.options.experimental = {"execution": {"scheduler_timing": True}}

# Submit jobs
sampler_job = sampler.run([isa_circuit])
result = sampler_job.result()

print(
    f">>> {' Job ID:':<10}  {sampler_job.job_id()} ({sampler_job.status()})"
)

>>>  Job ID:    d5kk3cn853es738e01dg (DONE)

다음으로 Circuit 스케줄 타이밍을 가져옵니다:

# Get the circuit schedule timing
result[0].metadata["compilation"]["scheduler_timing"]["timing"]

'main,rz_0,Qubit 0,929,0,shift_phase\nmain,sx_0,Qubit 0,929,8,play\nmain,sx_0,Qubit 0,933,0,shift_phase\nmain,rz_0,Qubit 0,937,0,shift_phase\nmain,barrier,Qubit 0,937,0,barrier\nmain,barrier,Qubit 0,937,0,barrier\nmain,barrier,Qubit 1,937,0,barrier\nmain,barrier,Qubit 2,937,0,barrier\nmain,barrier,Qubit 3,937,0,barrier\nmain,barrier,Qubit 4,937,0,barrier\nmain,barrier,Qubit 5,937,0,barrier\nmain,barrier,Qubit 6,937,0,barrier\nmain,barrier,Qubit 7,937,0,barrier\nmain,barrier,Qubit 8,937,0,barrier\nmain,barrier,Qubit 9,937,0,barrier\nmain,barrier,Qubit 10,937,0,barrier\nmain,barrier,Qubit 11,937,0,barrier\nmain,barrier,Qubit 12,937,0,barrier\nmain,barrier,Qubit 13,937,0,barrier\nmain,barrier,Qubit 14,937,0,barrier\nmain,barrier,Qubit 15,937,0,barrier\nmain,barrier,Qubit 16,937,0,barrier\nmain,barrier,Qubit 17,937,0,barrier\nmain,barrier,Qubit 18,937,0,barrier\nmain,barrier,Qubit 19,937,0,barrier\nmain,barrier,Qubit 20,937,0,barrier\nmain,barrier,Qubit 21,937,0,barrier\nmain,barrier,Qubit 22,937,0,barrier\nmain,barrier,Qubit 23,937,0,barrier\nmain,barrier,Qubit 24,937,0,barrier\nmain,barrier,Qubit 25,937,0,barrier\nmain,barrier,Qubit 26,937,0,barrier\nmain,barrier,Qubit 27,937,0,barrier\nmain,barrier,Qubit 28,937,0,barrier\nmain,barrier,Qubit 29,937,0,barrier\nmain,barrier,Qubit 30,937,0,barrier\nmain,barrier,Qubit 31,937,0,barrier\nmain,barrier,Qubit 32,937,0,barrier\nmain,barrier,Qubit 33,937,0,barrier\nmain,barrier,Qubit 34,937,0,barrier\nmain,barrier,Qubit 35,937,0,barrier\nmain,barrier,Qubit 36,937,0,barrier\nmain,barrier,Qubit 37,937,0,barrier\nmain,barrier,Qubit 38,937,0,barrier\nmain,barrier,Qubit 39,937,0,barrier\nmain,barrier,Qubit 40,937,0,barrier\nmain,barrier,Qubit 41,937,0,barrier\nmain,barrier,Qubit 42,937,0,barrier\nmain,barrier,Qubit 43,937,0,barrier\nmain,barrier,Qubit 44,937,0,barrier\nmain,barrier,Qubit 45,937,0,barrier\nmain,barrier,Qubit 46,937,0,barrier\nmain,barrier,Qubit 47,937,0,barrier\nmain,barrier,Qubit 48,937,0,barrier\nmain,barrier,Qubit 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102,937,0,barrier\nmain,barrier,Qubit 103,937,0,barrier\nmain,barrier,Qubit 104,937,0,barrier\nmain,barrier,Qubit 105,937,0,barrier\nmain,barrier,Qubit 106,937,0,barrier\nmain,barrier,Qubit 107,937,0,barrier\nmain,barrier,Qubit 108,937,0,barrier\nmain,barrier,Qubit 109,937,0,barrier\nmain,barrier,Qubit 110,937,0,barrier\nmain,barrier,Qubit 111,937,0,barrier\nmain,barrier,Qubit 112,937,0,barrier\nmain,barrier,Qubit 113,937,0,barrier\nmain,barrier,Qubit 114,937,0,barrier\nmain,barrier,Qubit 115,937,0,barrier\nmain,barrier,Qubit 116,937,0,barrier\nmain,barrier,Qubit 117,937,0,barrier\nmain,barrier,Qubit 118,937,0,barrier\nmain,barrier,Qubit 119,937,0,barrier\nmain,barrier,Qubit 120,937,0,barrier\nmain,barrier,Qubit 121,937,0,barrier\nmain,barrier,Qubit 122,937,0,barrier\nmain,barrier,Qubit 123,937,0,barrier\nmain,barrier,Qubit 124,937,0,barrier\nmain,barrier,Qubit 125,937,0,barrier\nmain,barrier,Qubit 126,937,0,barrier\nmain,barrier,Qubit 127,937,0,barrier\nmain,barrier,Qubit 128,937,0,barrier\nmain,barrier,Qubit 129,937,0,barrier\nmain,barrier,Qubit 130,937,0,barrier\nmain,barrier,Qubit 131,937,0,barrier\nmain,barrier,Qubit 132,937,0,barrier\nmain,measure_0,Qubit 0,937,64,play\nmain,measure_0,Qubit 0,1001,72,play\nmain,measure_0,AWGR13_0,1048,240,capture\nmain,measure_0,Qubit 0,1073,64,play\nmain,barrier,Qubit 0,1484,0,barrier\nmain,barrier,Qubit 0,1484,0,barrier\nmain,barrier,Qubit 1,1484,0,barrier\nmain,barrier,Qubit 2,1484,0,barrier\nmain,barrier,Qubit 3,1484,0,barrier\nmain,barrier,Qubit 4,1484,0,barrier\nmain,barrier,Qubit 5,1484,0,barrier\nmain,barrier,Qubit 6,1484,0,barrier\nmain,barrier,Qubit 7,1484,0,barrier\nmain,barrier,Qubit 8,1484,0,barrier\nmain,barrier,Qubit 9,1484,0,barrier\nmain,barrier,Qubit 10,1484,0,barrier\nmain,barrier,Qubit 11,1484,0,barrier\nmain,barrier,Qubit 12,1484,0,barrier\nmain,barrier,Qubit 13,1484,0,barrier\nmain,barrier,Qubit 14,1484,0,barrier\nmain,barrier,Qubit 15,1484,0,barrier\nmain,barrier,Qubit 16,1484,0,barrier\nmain,barrier,Qubit 17,1484,0,barrier\nmain,barrier,Qubit 18,1484,0,barrier\nmain,barrier,Qubit 19,1484,0,barrier\nmain,barrier,Qubit 20,1484,0,barrier\nmain,barrier,Qubit 21,1484,0,barrier\nmain,barrier,Qubit 22,1484,0,barrier\nmain,barrier,Qubit 23,1484,0,barrier\nmain,barrier,Qubit 24,1484,0,barrier\nmain,barrier,Qubit 25,1484,0,barrier\nmain,barrier,Qubit 26,1484,0,barrier\nmain,barrier,Qubit 27,1484,0,barrier\nmain,barrier,Qubit 28,1484,0,barrier\nmain,barrier,Qubit 29,1484,0,barrier\nmain,barrier,Qubit 30,1484,0,barrier\nmain,barrier,Qubit 31,1484,0,barrier\nmain,barrier,Qubit 32,1484,0,barrier\nmain,barrier,Qubit 33,1484,0,barrier\nmain,barrier,Qubit 34,1484,0,barrier\nmain,barrier,Qubit 35,1484,0,barrier\nmain,barrier,Qubit 36,1484,0,barrier\nmain,barrier,Qubit 37,1484,0,barrier\nmain,barrier,Qubit 38,1484,0,barrier\nmain,barrier,Qubit 39,1484,0,barrier\nmain,barrier,Qubit 40,1484,0,barrier\nmain,barrier,Qubit 41,1484,0,barrier\nmain,barrier,Qubit 42,1484,0,barrier\nmain,barrier,Qubit 43,1484,0,barrier\nmain,barrier,Qubit 44,1484,0,barrier\nmain,barrier,Qubit 45,1484,0,barrier\nmain,barrier,Qubit 46,1484,0,barrier\nmain,barrier,Qubit 47,1484,0,barrier\nmain,barrier,Qubit 48,1484,0,barrier\nmain,barrier,Qubit 49,1484,0,barrier\nmain,barrier,Qubit 50,1484,0,barrier\nmain,barrier,Qubit 51,1484,0,barrier\nmain,barrier,Qubit 52,1484,0,barrier\nmain,barrier,Qubit 53,1484,0,barrier\nmain,barrier,Qubit 54,1484,0,barrier\nmain,barrier,Qubit 55,1484,0,barrier\nmain,barrier,Qubit 56,1484,0,barrier\nmain,barrier,Qubit 57,1484,0,barrier\nmain,barrier,Qubit 58,1484,0,barrier\nmain,barrier,Qubit 59,1484,0,barrier\nmain,barrier,Qubit 60,1484,0,barrier\nmain,barrier,Qubit 61,1484,0,barrier\nmain,barrier,Qubit 62,1484,0,barrier\nmain,barrier,Qubit 63,1484,0,barrier\nmain,barrier,Qubit 64,1484,0,barrier\nmain,barrier,Qubit 65,1484,0,barrier\nmain,barrier,Qubit 66,1484,0,barrier\nmain,barrier,Qubit 67,1484,0,barrier\nmain,barrier,Qubit 68,1484,0,barrier\nmain,barrier,Qubit 69,1484,0,barrier\nmain,barrier,Qubit 70,1484,0,barrier\nmain,barrier,Qubit 71,1484,0,barrier\nmain,barrier,Qubit 72,1484,0,barrier\nmain,barrier,Qubit 73,1484,0,barrier\nmain,barrier,Qubit 74,1484,0,barrier\nmain,barrier,Qubit 75,1484,0,barrier\nmain,barrier,Qubit 76,1484,0,barrier\nmain,barrier,Qubit 77,1484,0,barrier\nmain,barrier,Qubit 78,1484,0,barrier\nmain,barrier,Qubit 79,1484,0,barrier\nmain,barrier,Qubit 80,1484,0,barrier\nmain,barrier,Qubit 81,1484,0,barrier\nmain,barrier,Qubit 82,1484,0,barrier\nmain,barrier,Qubit 83,1484,0,barrier\nmain,barrier,Qubit 84,1484,0,barrier\nmain,barrier,Qubit 85,1484,0,barrier\nmain,barrier,Qubit 86,1484,0,barrier\nmain,barrier,Qubit 87,1484,0,barrier\nmain,barrier,Qubit 88,1484,0,barrier\nmain,barrier,Qubit 89,1484,0,barrier\nmain,barrier,Qubit 90,1484,0,barrier\nmain,barrier,Qubit 91,1484,0,barrier\nmain,barrier,Qubit 92,1484,0,barrier\nmain,barrier,Qubit 93,1484,0,barrier\nmain,barrier,Qubit 94,1484,0,barrier\nmain,barrier,Qubit 95,1484,0,barrier\nmain,barrier,Qubit 96,1484,0,barrier\nmain,barrier,Qubit 97,1484,0,barrier\nmain,barrier,Qubit 98,1484,0,barrier\nmain,barrier,Qubit 99,1484,0,barrier\nmain,barrier,Qubit 100,1484,0,barrier\nmain,barrier,Qubit 101,1484,0,barrier\nmain,barrier,Qubit 102,1484,0,barrier\nmain,barrier,Qubit 103,1484,0,barrier\nmain,barrier,Qubit 104,1484,0,barrier\nmain,barrier,Qubit 105,1484,0,barrier\nmain,barrier,Qubit 106,1484,0,barrier\nmain,barrier,Qubit 107,1484,0,barrier\nmain,barrier,Qubit 108,1484,0,barrier\nmain,barrier,Qubit 109,1484,0,barrier\nmain,barrier,Qubit 110,1484,0,barrier\nmain,barrier,Qubit 111,1484,0,barrier\nmain,barrier,Qubit 112,1484,0,barrier\nmain,barrier,Qubit 113,1484,0,barrier\nmain,barrier,Qubit 114,1484,0,barrier\nmain,barrier,Qubit 115,1484,0,barrier\nmain,barrier,Qubit 116,1484,0,barrier\nmain,barrier,Qubit 117,1484,0,barrier\nmain,barrier,Qubit 118,1484,0,barrier\nmain,barrier,Qubit 119,1484,0,barrier\nmain,barrier,Qubit 120,1484,0,barrier\nmain,barrier,Qubit 121,1484,0,barrier\nmain,barrier,Qubit 122,1484,0,barrier\nmain,barrier,Qubit 123,1484,0,barrier\nmain,barrier,Qubit 124,1484,0,barrier\nmain,barrier,Qubit 125,1484,0,barrier\nmain,barrier,Qubit 126,1484,0,barrier\nmain,barrier,Qubit 127,1484,0,barrier\nmain,barrier,Qubit 128,1484,0,barrier\nmain,barrier,Qubit 129,1484,0,barrier\nmain,barrier,Qubit 130,1484,0,barrier\nmain,barrier,Qubit 131,1484,0,barrier\nmain,barrier,Qubit 132,1484,0,barrier\nmain,broadcast,Hub,1048,436,broadcast\nmain,receive,Receive,1484,7,receive\nthen,x_0,Qubit 0,1499,8,play\nmain,barrier,Qubit 0,1516,0,barrier\nmain,barrier,Qubit 0,1516,0,barrier\nmain,barrier,Qubit 1,1516,0,barrier\nmain,barrier,Qubit 2,1516,0,barrier\nmain,barrier,Qubit 3,1516,0,barrier\nmain,barrier,Qubit 4,1516,0,barrier\nmain,barrier,Qubit 5,1516,0,barrier\nmain,barrier,Qubit 6,1516,0,barrier\nmain,barrier,Qubit 7,1516,0,barrier\nmain,barrier,Qubit 8,1516,0,barrier\nmain,barrier,Qubit 9,1516,0,barrier\nmain,barrier,Qubit 10,1516,0,barrier\nmain,barrier,Qubit 11,1516,0,barrier\nmain,barrier,Qubit 12,1516,0,barrier\nmain,barrier,Qubit 13,1516,0,barrier\nmain,barrier,Qubit 14,1516,0,barrier\nmain,barrier,Qubit 15,1516,0,barrier\nmain,barrier,Qubit 16,1516,0,barrier\nmain,barrier,Qubit 17,1516,0,barrier\nmain,barrier,Qubit 18,1516,0,barrier\nmain,barrier,Qubit 19,1516,0,barrier\nmain,barrier,Qubit 20,1516,0,barrier\nmain,barrier,Qubit 21,1516,0,barrier\nmain,barrier,Qubit 22,1516,0,barrier\nmain,barrier,Qubit 23,1516,0,barrier\nmain,barrier,Qubit 24,1516,0,barrier\nmain,barrier,Qubit 25,1516,0,barrier\nmain,barrier,Qubit 26,1516,0,barrier\nmain,barrier,Qubit 27,1516,0,barrier\nmain,barrier,Qubit 28,1516,0,barrier\nmain,barrier,Qubit 29,1516,0,barrier\nmain,barrier,Qubit 30,1516,0,barrier\nmain,barrier,Qubit 31,1516,0,barrier\nmain,barrier,Qubit 32,1516,0,barrier\nmain,barrier,Qubit 33,1516,0,barrier\nmain,barrier,Qubit 34,1516,0,barrier\nmain,barrier,Qubit 35,1516,0,barrier\nmain,barrier,Qubit 36,1516,0,barrier\nmain,barrier,Qubit 37,1516,0,barrier\nmain,barrier,Qubit 38,1516,0,barrier\nmain,barrier,Qubit 39,1516,0,barrier\nmain,barrier,Qubit 40,1516,0,barrier\nmain,barrier,Qubit 41,1516,0,barrier\nmain,barrier,Qubit 42,1516,0,barrier\nmain,barrier,Qubit 43,1516,0,barrier\nmain,barrier,Qubit 44,1516,0,barrier\nmain,barrier,Qubit 45,1516,0,barrier\nmain,barrier,Qubit 46,1516,0,barrier\nmain,barrier,Qubit 47,1516,0,barrier\nmain,barrier,Qubit 48,1516,0,barrier\nmain,barrier,Qubit 49,1516,0,barrier\nmain,barrier,Qubit 50,1516,0,barrier\nmain,barrier,Qubit 51,1516,0,barrier\nmain,barrier,Qubit 52,1516,0,barrier\nmain,barrier,Qubit 53,1516,0,barrier\nmain,barrier,Qubit 54,1516,0,barrier\nmain,barrier,Qubit 55,1516,0,barrier\nmain,barrier,Qubit 56,1516,0,barrier\nmain,barrier,Qubit 57,1516,0,barrier\nmain,barrier,Qubit 58,1516,0,barrier\nmain,barrier,Qubit 59,1516,0,barrier\nmain,barrier,Qubit 60,1516,0,barrier\nmain,barrier,Qubit 61,1516,0,barrier\nmain,barrier,Qubit 62,1516,0,barrier\nmain,barrier,Qubit 63,1516,0,barrier\nmain,barrier,Qubit 64,1516,0,barrier\nmain,barrier,Qubit 65,1516,0,barrier\nmain,barrier,Qubit 66,1516,0,barrier\nmain,barrier,Qubit 67,1516,0,barrier\nmain,barrier,Qubit 68,1516,0,barrier\nmain,barrier,Qubit 69,1516,0,barrier\nmain,barrier,Qubit 70,1516,0,barrier\nmain,barrier,Qubit 71,1516,0,barrier\nmain,barrier,Qubit 72,1516,0,barrier\nmain,barrier,Qubit 73,1516,0,barrier\nmain,barrier,Qubit 74,1516,0,barrier\nmain,barrier,Qubit 75,1516,0,barrier\nmain,barrier,Qubit 76,1516,0,barrier\nmain,barrier,Qubit 77,1516,0,barrier\nmain,barrier,Qubit 78,1516,0,barrier\nmain,barrier,Qubit 79,1516,0,barrier\nmain,barrier,Qubit 80,1516,0,barrier\nmain,barrier,Qubit 81,1516,0,barrier\nmain,barrier,Qubit 82,1516,0,barrier\nmain,barrier,Qubit 83,1516,0,barrier\nmain,barrier,Qubit 84,1516,0,barrier\nmain,barrier,Qubit 85,1516,0,barrier\nmain,barrier,Qubit 86,1516,0,barrier\nmain,barrier,Qubit 87,1516,0,barrier\nmain,barrier,Qubit 88,1516,0,barrier\nmain,barrier,Qubit 89,1516,0,barrier\nmain,barrier,Qubit 90,1516,0,barrier\nmain,barrier,Qubit 91,1516,0,barrier\nmain,barrier,Qubit 92,1516,0,barrier\nmain,barrier,Qubit 93,1516,0,barrier\nmain,barrier,Qubit 94,1516,0,barrier\nmain,barrier,Qubit 95,1516,0,barrier\nmain,barrier,Qubit 96,1516,0,barrier\nmain,barrier,Qubit 97,1516,0,barrier\nmain,barrier,Qubit 98,1516,0,barrier\nmain,barrier,Qubit 99,1516,0,barrier\nmain,barrier,Qubit 100,1516,0,barrier\nmain,barrier,Qubit 101,1516,0,barrier\nmain,barrier,Qubit 102,1516,0,barrier\nmain,barrier,Qubit 103,1516,0,barrier\nmain,barrier,Qubit 104,1516,0,barrier\nmain,barrier,Qubit 105,1516,0,barrier\nmain,barrier,Qubit 106,1516,0,barrier\nmain,barrier,Qubit 107,1516,0,barrier\nmain,barrier,Qubit 108,1516,0,barrier\nmain,barrier,Qubit 109,1516,0,barrier\nmain,barrier,Qubit 110,1516,0,barrier\nmain,barrier,Qubit 111,1516,0,barrier\nmain,barrier,Qubit 112,1516,0,barrier\nmain,barrier,Qubit 113,1516,0,barrier\nmain,barrier,Qubit 114,1516,0,barrier\nmain,barrier,Qubit 115,1516,0,barrier\nmain,barrier,Qubit 116,1516,0,barrier\nmain,barrier,Qubit 117,1516,0,barrier\nmain,barrier,Qubit 118,1516,0,barrier\nmain,barrier,Qubit 119,1516,0,barrier\nmain,barrier,Qubit 120,1516,0,barrier\nmain,barrier,Qubit 121,1516,0,barrier\nmain,barrier,Qubit 122,1516,0,barrier\nmain,barrier,Qubit 123,1516,0,barrier\nmain,barrier,Qubit 124,1516,0,barrier\nmain,barrier,Qubit 125,1516,0,barrier\nmain,barrier,Qubit 126,1516,0,barrier\nmain,barrier,Qubit 127,1516,0,barrier\nmain,barrier,Qubit 128,1516,0,barrier\nmain,barrier,Qubit 129,1516,0,barrier\nmain,barrier,Qubit 130,1516,0,barrier\nmain,barrier,Qubit 131,1516,0,barrier\nmain,barrier,Qubit 132,1516,0,barrier\nmain,measure_0,Qubit 0,1516,64,play\nmain,measure_0,Qubit 0,1580,72,play\nmain,measure_0,AWGR13_0,1627,240,capture\nmain,measure_0,Qubit 0,1652,64,play\nmain,barrier,Qubit 0,1906,0,barrier\nmain,barrier,Qubit 0,1906,0,barrier\nmain,barrier,Qubit 1,1906,0,barrier\nmain,barrier,Qubit 2,1906,0,barrier\nmain,barrier,Qubit 3,1906,0,barrier\nmain,barrier,Qubit 4,1906,0,barrier\nmain,barrier,Qubit 5,1906,0,barrier\nmain,barrier,Qubit 6,1906,0,barrier\nmain,barrier,Qubit 7,1906,0,barrier\nmain,barrier,Qubit 8,1906,0,barrier\nmain,barrier,Qubit 9,1906,0,barrier\nmain,barrier,Qubit 10,1906,0,barrier\nmain,barrier,Qubit 11,1906,0,barrier\nmain,barrier,Qubit 12,1906,0,barrier\nmain,barrier,Qubit 13,1906,0,barrier\nmain,barrier,Qubit 14,1906,0,barrier\nmain,barrier,Qubit 15,1906,0,barrier\nmain,barrier,Qubit 16,1906,0,barrier\nmain,barrier,Qubit 17,1906,0,barrier\nmain,barrier,Qubit 18,1906,0,barrier\nmain,barrier,Qubit 19,1906,0,barrier\nmain,barrier,Qubit 20,1906,0,barrier\nmain,barrier,Qubit 21,1906,0,barrier\nmain,barrier,Qubit 22,1906,0,barrier\nmain,barrier,Qubit 23,1906,0,barrier\nmain,barrier,Qubit 24,1906,0,barrier\nmain,barrier,Qubit 25,1906,0,barrier\nmain,barrier,Qubit 26,1906,0,barrier\nmain,barrier,Qubit 27,1906,0,barrier\nmain,barrier,Qubit 28,1906,0,barrier\nmain,barrier,Qubit 29,1906,0,barrier\nmain,barrier,Qubit 30,1906,0,barrier\nmain,barrier,Qubit 31,1906,0,barrier\nmain,barrier,Qubit 32,1906,0,barrier\nmain,barrier,Qubit 33,1906,0,barrier\nmain,barrier,Qubit 34,1906,0,barrier\nmain,barrier,Qubit 35,1906,0,barrier\nmain,barrier,Qubit 36,1906,0,barrier\nmain,barrier,Qubit 37,1906,0,barrier\nmain,barrier,Qubit 38,1906,0,barrier\nmain,barrier,Qubit 39,1906,0,barrier\nmain,barrier,Qubit 40,1906,0,barrier\nmain,barrier,Qubit 41,1906,0,barrier\nmain,barrier,Qubit 42,1906,0,barrier\nmain,barrier,Qubit 43,1906,0,barrier\nmain,barrier,Qubit 44,1906,0,barrier\nmain,barrier,Qubit 45,1906,0,barrier\nmain,barrier,Qubit 46,1906,0,barrier\nmain,barrier,Qubit 47,1906,0,barrier\nmain,barrier,Qubit 48,1906,0,barrier\nmain,barrier,Qubit 49,1906,0,barrier\nmain,barrier,Qubit 50,1906,0,barrier\nmain,barrier,Qubit 51,1906,0,barrier\nmain,barrier,Qubit 52,1906,0,barrier\nmain,barrier,Qubit 53,1906,0,barrier\nmain,barrier,Qubit 54,1906,0,barrier\nmain,barrier,Qubit 55,1906,0,barrier\nmain,barrier,Qubit 56,1906,0,barrier\nmain,barrier,Qubit 57,1906,0,barrier\nmain,barrier,Qubit 58,1906,0,barrier\nmain,barrier,Qubit 59,1906,0,barrier\nmain,barrier,Qubit 60,1906,0,barrier\nmain,barrier,Qubit 61,1906,0,barrier\nmain,barrier,Qubit 62,1906,0,barrier\nmain,barrier,Qubit 63,1906,0,barrier\nmain,barrier,Qubit 64,1906,0,barrier\nmain,barrier,Qubit 65,1906,0,barrier\nmain,barrier,Qubit 66,1906,0,barrier\nmain,barrier,Qubit 67,1906,0,barrier\nmain,barrier,Qubit 68,1906,0,barrier\nmain,barrier,Qubit 69,1906,0,barrier\nmain,barrier,Qubit 70,1906,0,barrier\nmain,barrier,Qubit 71,1906,0,barrier\nmain,barrier,Qubit 72,1906,0,barrier\nmain,barrier,Qubit 73,1906,0,barrier\nmain,barrier,Qubit 74,1906,0,barrier\nmain,barrier,Qubit 75,1906,0,barrier\nmain,barrier,Qubit 76,1906,0,barrier\nmain,barrier,Qubit 77,1906,0,barrier\nmain,barrier,Qubit 78,1906,0,barrier\nmain,barrier,Qubit 79,1906,0,barrier\nmain,barrier,Qubit 80,1906,0,barrier\nmain,barrier,Qubit 81,1906,0,barrier\nmain,barrier,Qubit 82,1906,0,barrier\nmain,barrier,Qubit 83,1906,0,barrier\nmain,barrier,Qubit 84,1906,0,barrier\nmain,barrier,Qubit 85,1906,0,barrier\nmain,barrier,Qubit 86,1906,0,barrier\nmain,barrier,Qubit 87,1906,0,barrier\nmain,barrier,Qubit 88,1906,0,barrier\nmain,barrier,Qubit 89,1906,0,barrier\nmain,barrier,Qubit 90,1906,0,barrier\nmain,barrier,Qubit 91,1906,0,barrier\nmain,barrier,Qubit 92,1906,0,barrier\nmain,barrier,Qubit 93,1906,0,barrier\nmain,barrier,Qubit 94,1906,0,barrier\nmain,barrier,Qubit 95,1906,0,barrier\nmain,barrier,Qubit 96,1906,0,barrier\nmain,barrier,Qubit 97,1906,0,barrier\nmain,barrier,Qubit 98,1906,0,barrier\nmain,barrier,Qubit 99,1906,0,barrier\nmain,barrier,Qubit 100,1906,0,barrier\nmain,barrier,Qubit 101,1906,0,barrier\nmain,barrier,Qubit 102,1906,0,barrier\nmain,barrier,Qubit 103,1906,0,barrier\nmain,barrier,Qubit 104,1906,0,barrier\nmain,barrier,Qubit 105,1906,0,barrier\nmain,barrier,Qubit 106,1906,0,barrier\nmain,barrier,Qubit 107,1906,0,barrier\nmain,barrier,Qubit 108,1906,0,barrier\nmain,barrier,Qubit 109,1906,0,barrier\nmain,barrier,Qubit 110,1906,0,barrier\nmain,barrier,Qubit 111,1906,0,barrier\nmain,barrier,Qubit 112,1906,0,barrier\nmain,barrier,Qubit 113,1906,0,barrier\nmain,barrier,Qubit 114,1906,0,barrier\nmain,barrier,Qubit 115,1906,0,barrier\nmain,barrier,Qubit 116,1906,0,barrier\nmain,barrier,Qubit 117,1906,0,barrier\nmain,barrier,Qubit 118,1906,0,barrier\nmain,barrier,Qubit 119,1906,0,barrier\nmain,barrier,Qubit 120,1906,0,barrier\nmain,barrier,Qubit 121,1906,0,barrier\nmain,barrier,Qubit 122,1906,0,barrier\nmain,barrier,Qubit 123,1906,0,barrier\nmain,barrier,Qubit 124,1906,0,barrier\nmain,barrier,Qubit 125,1906,0,barrier\nmain,barrier,Qubit 126,1906,0,barrier\nmain,barrier,Qubit 127,1906,0,barrier\nmain,barrier,Qubit 128,1906,0,barrier\nmain,barrier,Qubit 129,1906,0,barrier\nmain,barrier,Qubit 130,1906,0,barrier\nmain,barrier,Qubit 131,1906,0,barrier\nmain,barrier,Qubit 132,1906,0,barrier\nmain,barrier,Qubit 0,1906,0,barrier\n'

마지막으로 타이밍을 시각화하고 저장할 수 있습니다:

from qiskit_ibm_runtime.visualization import draw_circuit_schedule_timing

circuit_schedule = result[0].metadata["compilation"]["scheduler_timing"][
    "timing"
]
fig = draw_circuit_schedule_timing(
    circuit_schedule=circuit_schedule,
    included_channels=None,
    filter_readout_channels=False,
    filter_barriers=False,
    width=1000,
)

# Uncomment the following line to display the figure
# fig.show(renderer="notebook")

# Save to a file
# fig.write_html("scheduler_timing.html")

다음 단계

추천

• 고전적 피드포워드 및 제어 흐름 (동적 Circuit)
• Circuit 시각화